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Verilog - Unique Simon Says Game on FPGA

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This little game is a fun way to explore the basics of writing hardware description language code on a micro-chip. We are using an FPGA and the verilog language.


About Verilog and The Project:

Verilog is mostly used as a test bench language to test out and stress hardware. You can also use verilog to program electronics hardware too. The project was created to demonstrate simple Moore state machine while utilizing input and output pins on the FPGA. More information can be found in the report and video demonstration below. 


The Report:

Normally I hardly share these kind of reports, but in order to understand what I did and why I did the things I did for the FPGA, you have to understand my logic because I wrote the code. The board.ucf file which is the user configuration file was just a standard library for initializing the pins, clock, and such (nothing fancy) so I don't think it's necessary to include it here. Here is the report in pdf format straight from my Google Drive! Please note that the code in the report is old: please look at the source code section below.

 


The Video Demonstration:

The video below shows the little game. I was going to add additional modes such as normal mode and hard mode but didn't have time to add them when I was working on the project. I still didn't add them because it really isn't a useful project for the most part. Learning about how hardware works and programming it was a fun experience and I enjoyed the class I took surrounding this topic. An issue with the code, in which I could not figure out is that sometimes it would work properly and light-up the correct number of LEDs and sometimes it would not. I have no intention of figuring it out at this time, but it probably has something to do with the clock.


Source Code:

The code is not optimized at all and you can definately decrease the code to a lesser amount. I just thought and put it together in the final days before submitting this project...

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Conclusion:

It was a fun project and I hope you found this article useful and maybe you can improve it or learn something from it. Thank you :).

Tags: Computer Science, Verilog

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